A Method for Leakage Current and Power Reduction of Buffer in 65-nm CMOS Technology Based on the Pileup-Effect

In small-size Complementary Metal Oxide Semiconductor (CMOS) technology, the size of Very Large-Scale Integration (VLSI) below 90nm becomes higher and due to enhancement short channel effect transistors. CMOS Buffer is a very common circuit unit in VLSI. this paper, Pileup transistor (PET) proposed reduce subthreshold leakage current buffer. The main principle PET technology voltage difference between gate source drain by lowering so as current. Through simulation-based on Cadence Taiwan Manufacturing Company (TSMC) N65 library, can power consumption about one-twelfth original while maintaining function has also been found transition state 40%.